Non-destructive self-reference spin-transfer torque memory

ABSTRACT

A non-destructive self-reference spin-transfer torque memory unit is disclosed.

CROSS-REFERENCE

This application is a divisional of application Ser. No. 13/349,044, filed Jan. 12, 2012, which is continuation of application Ser. No. 12/147,727, filed Jun. 27, 2008, now U.S. Pat. No. 8,116,123, issued Feb. 14, 2012, the contents of each is hereby incorporated by reference in its entirety.

BACKGROUND

Fast growth of the pervasive computing and handheld/communication industry generates exploding demand for high capacity nonvolatile solid-state data storage devices. It is believed that nonvolatile memories, especially flash memory, will replace DRAM to occupy the biggest share of memory market by 2009. However, flash memory has several drawbacks such as slow access speed (˜ms write and ˜50-100 ns read), limited endurance (˜10³-10⁴ programming cycles), and the integration difficulty in system-on-chip (SoC). Flash memory (NAND or NOR) also faces significant scaling problems at 32 nm node and beyond.

Magneto-resistive Random Access Memory (MRAM) is another promising candidate for future nonvolatile and universal memory. MRAM features non-volatility, fast writing/reading speed (<10 ns), almost unlimited programming endurance (>10¹⁵ cycles) and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). Data storage is realized by switching the resistance of MTJ between a high-resistance state and a low-resistance state. MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes severer. Hence, the incurred high power consumption limits the scaling of conventional MRAM.

Recently, a new write mechanism, which is based upon spin polarization current induced magnetization switching, was introduced to the MRAM design. This new MRAM design, called Spin-Torque Transfer RAM (STRAM), uses a (bidirectional) current through the MTJ to realize the resistance switching. Therefore, the switching mechanism of STRAM is constrained locally and STRAM is believed to have a better scaling property than the conventional MRAM.

However, many yield-limiting factors must be overcome before STRAM enters the production stage. One challenge is the large MTJ resistance variation, which is exponentially dependent on the thickness of oxide barrier in it. For example, increasing the thickness of oxide barrier from 14 Angstroms to 14.1 Angstroms changes the MTJ resistance by 8%. This large MTJ resistance variation can create problems during a read operation of the MTJ.

BRIEF SUMMARY

The present disclosure relates to spin-transfer torque random access memory self-reference non-destructive read operations and apparatus for the same. In particular, present disclosure relates to a spin-transfer torque random access memory self-reference non-destructive read operation that overcomes the large variation of MTJ resistance.

One illustrative method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Another illustrative method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first capacitor. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second capacitor and a third capacitor. The first read current is less than the second read current and the second capacitor and the third capacitor are electrically connected in series. The stored first bit line read voltage is then compared with the stored second bit line read voltage. If the first bit line read voltage is substantially the same as or less than the stored second bit line read voltage then the first resistance state is determined to be a low resistance state. However, if the first bit line read voltage is not substantially the same as or greater than the stored second bit line read voltage then the first resistance state is determined to be a high resistance state.

An illustrative spin-transfer torque memory apparatus includes a magnetic tunnel junction data cell having a ferromagnetic free layer and a ferromagnetic reference layer separated by a oxide barrier layer. The magnetic tunnel junction data cell is electrically between a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. An adjustable current driver is electrically coupled to the bit line. The adjustable current driver is configured to provide a first read current and a second read current through the magnetic tunnel junction data cell. A first voltage storage device is electrically coupled to the bit line and is configured to store a first bit line voltage formed by the first read current. A second voltage storage device is electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current and a third voltage storage device is electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current. The second voltage storage device and the third voltage storage device are electrically connected in series. A differential sense amplifier is electrically coupled to the first voltage storage device and is also electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device. The differential sense amplifier is configured to compare the first bit line voltage with the second bit line voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:

FIG. 1 is a cross-sectional schematic diagram of an illustrative spin-transfer torque MTJ memory unit in the low resistance state;

FIG. 2 is a cross-sectional schematic diagram of another spin-transfer torque MTJ memory unit in the high resistance state;

FIG. 3 is a graph of a static R-V (resistance-voltage) curve of a spin-transfer torque MTJ memory unit;

FIG. 4 is a schematic circuit diagram of a spin-transfer torque MTJ memory unit;

FIG. 5 is a schematic circuit diagram of an illustrative spin-transfer torque MTJ memory apparatus;

FIG. 6 is a graph of I-R (current-resistance) curves of the MTJ high resistance state and low resistance state;

FIG. 7 is a schematic circuit diagram of an illustrative adjustable current driver for FIG. 5;

FIG. 8 is a schematic circuit diagram of an illustrative differential sense amplifier for FIG. 5;

FIG. 9 is a timing diagram for the illustrative spin-transfer torque MTJ memory apparatus of FIG. 5; and

FIG. 10 is a flow diagram of an illustrative self-reference reading method.

The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.

The recitation of numerical ranges by endpoints includes all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.

As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

The present disclosure relates to spin-transfer torque memory apparatus and self-reference non-destructive read schemes. In particular, present disclosure relates to non-destructive self-reference reading methods that determine whether a spin-transfer torque memory unit has a high resistance state or low resistance state data state, without disturbing the original data resistance state of the spin-transfer torque memory unit. The apparatus and methods described herein ensure that the value of the spin-transfer torque memory unit can be determined regardless of the resistance variation of the spin-transfer torque memory units within a memory array. The read voltage of the spin-transfer torque memory unit at a first read current and a second read current are stored sequentially and compared to detect the resistance state or data state of the spin-transfer torque memory unit. Preserving the original resistance state eliminates the “standard-value-write” and “write-back” steps that are required in “destructive self-reference” read methods. Destructive self-reference read methods wipe out the original value stored in the spin-transfer torque memory unit when writing the standard value into it. These destructive self-reference read methods introduce reliability issues for non-volatile memory as the original stored data value can be lost if the chip power is shut down before the write back operation completes. Thus the disclosed read methods shorten the read operation latency and improve the reliability of the non-volatile data. While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.

FIG. 1 is a cross-sectional schematic diagram of an illustrative spin-transfer torque MTJ memory unit 10 in the low resistance state and FIG. 2 is a cross-sectional schematic diagram of another spin-transfer torque MTJ memory unit 10 in the high resistance state. A magnetic tunnel junction (MTJ) memory unit 10 includes a ferromagnetic free layer 12 and a ferromagnetic reference (i.e., pinned) layer 14. The ferromagnetic free layer 12 and a ferromagnetic reference layer 14 are separated by an oxide barrier layer 13 or tunnel barrier. A first electrode 15 is in electrical contact with the ferromagnetic free layer 12 and a second electrode 16 is in electrical contact with the ferromagnetic reference layer 14. The ferromagnetic layers 12, 14 may be made of any useful ferromagnetic (FM) alloys such as, for example, Fe, Co, Ni and the insulating barrier layer 13 may be made of an electrically insulating material such as, for example an oxide material (e.g., Al₂O₃ or MgO). Other suitable materials may also be used.

The electrodes 15, 16 electrically connect the ferromagnetic layers 12, 14 to a control circuit providing read and write currents through the ferromagnetic layers 12, 14. The resistance across the spin-transfer torque MTJ memory unit 10 is determined by the relative orientation of the magnetization vectors or magnetization orientations of the ferromagnetic layers 12, 14. The magnetization direction of the ferromagnetic reference layer 14 is pinned in a predetermined direction while the magnetization direction of the ferromagnetic free layer 12 is free to rotate under the influence of a spin torque. Pinning of the ferromagnetic reference layer 14 may be achieved through, e.g., the use of exchange bias with an antiferromagnetically ordered material such as PtMn, IrMn and others.

FIG. 1 illustrates the spin-transfer torque MTJ memory unit 10 in the low resistance state where the magnetization orientation of the ferromagnetic free layer 12 is parallel and in the same direction of the magnetization orientation of the ferromagnetic reference layer 14. This is termed the low resistance state or “0” data state. FIG. 2 illustrates the spin-transfer torque MTJ memory unit 10 in the high resistance state where the magnetization orientation of the ferromagnetic free layer 12 is anti-parallel and in the opposite direction of the magnetization orientation of the ferromagnetic reference layer 14. This is termed the high resistance state or “1” data state.

Switching the resistance state and hence the data state of the MTJ memory unit 10 via spin-transfer occurs when a current, passing through a magnetic layer of the MTJ memory unit 10, becomes spin polarized and imparts a spin torque on the free layer 12 of the MTJ 10. When a sufficient spin torque is applied to the free layer 12, the magnetization orientation of the free layer 12 can be switched between two opposite directions and accordingly the MTJ 10 can be switched between the parallel state (i.e., low resistance state or “0” data state) and anti-parallel state (i.e., high resistance state or “1” data state) depending on the direction of the current.

The illustrative spin-transfer torque MTJ memory unit 10 may be used to construct a memory device that includes multiple MTJ memory units where a data bit is stored in spin-transfer torque MTJ memory unit by changing the relative magnetization state of the free magnetic layer 12 with respect to the pinned magnetic layer 14. The stored data bit can be read out by measuring the resistance of the cell which changes with the magnetization direction of the free layer relative to the pinned magnetic layer. In order for the spin-transfer torque MTJ memory unit 10 to have the characteristics of a non-volatile random access memory, the free layer exhibits thermal stability against random fluctuations so that the orientation of the free layer is changed only when it is controlled to make such a change. This thermal stability can be achieved via the magnetic anisotropy using different methods, e.g., varying the bit size, shape, and crystalline anisotropy. Additional anisotropy can be obtained through magnetic coupling to other magnetic layers either through exchange or magnetic fields. Generally, the anisotropy causes a soft and hard axis to form in thin magnetic layers. The hard and soft axes are defined by the magnitude of the external energy, usually in the form of a magnetic field, needed to fully rotate (saturate) the direction of the magnetization in that direction, with the hard axis requiring a higher saturation magnetic field.

FIG. 3 is a graph of a static R-V sweep curve of a spin-transfer torque MTJ memory unit. When applying a positive voltage on the second electrode 16 in FIG. 1 or 2, the MTJ 10 enters the positive applied voltage region in FIG. 3 and switches from the high resistance state (FIG. 2) to the low resistance state (FIG. 1). When applying a positive voltage on the first electrode 15 in FIG. 1 or 2, the MTJ 10 enters the negative applied voltage region in FIG. 3. The resistance of the MTJ switches from the low resistance state (FIG. 1) to the high resistance state (FIG. 2).

Let R_(H) and R_(L) denote the high and low MTJ resistance, respectively. We define the Tunneling Magneto Resistance Ratio (TMR) as TMR=(R_(H)−R_(L))/R_(L). Here R_(H), R_(L) and TMR are determined by also the sensing current or voltage, as shown in FIG. 3. Generally, a large TMR makes it easier to distinguish the two resistance states of the MTJ.

FIG. 4 is a schematic diagram of a spin-transfer torque MTJ memory unit MTJ. The spin-transfer torque MTJ memory unit MTJ is electrically connected in series to a transistor such as, for example, a NMOS transistor. The opposing side of the spin-transfer torque MTJ memory unit MTJ is electrically connected to a bit line BL. The transistor is electrically coupled to a source line SL and a word line WL. The MTJ is usually modeled as a variable resistor in circuit schematic, as shown in FIG. 4.

Some spin-transfer torque MTJ memory units MTJ use a sensing scheme that relies on a standard reference voltage to read the resistance value of the MTJ. However, such a sense scheme requires that the maximum bit line voltage for the low resistance state be less than the minimum bit line voltage for the high resistance state for all of the MTJs in a memory array, which may not true when the variation of the MTJ resistance is large.

FIG. 5 is a schematic circuit diagram of an illustrative spin-transfer torque MTJ memory apparatus. The apparatus includes a magnetic tunnel junction data cell MTJ including a ferromagnetic free layer and a ferromagnetic reference layer separated by a oxide barrier layer, as described above. The magnetic tunnel junction data cell is electrically between a bit line BL and a source line SL. The magnetic tunnel junction data cell MTJ is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell MTJ. A cell transistor allows read and write current to flow through the magnetic tunnel junction data cell MTJ. A gate contact of the cell transistor is electrically coupled to a word line WL to allow selection of the particular cell transistor and associated magnetic tunnel junction data cell MTJ.

An adjustable current driver (an illustrative schematic diagram is shown in FIG. 7) is electrically coupled to the bit line, the adjustable current driver configured to provide a first read current I_(R1) and a second read current I_(R2) through the magnetic tunnel junction data cell MTJ. A first voltage storage device C1 is electrically coupled to the bit line BL and configured to store a first bit line voltage V_(BL1) formed by the first read current I_(R1). A second voltage storage device C2 is electrically coupled to the bit line BL and configured to store a second bit line voltage V_(BL2) formed by the second read current I_(R2). In many embodiments, the second voltage storage device C2 is a second voltage storage device C21 electrically coupled to the bit line BL and a third voltage storage device C22 electrically coupled to the bit line BL, and the second voltage storage device C21 and the third voltage storage device C22 are electrically connected in series, as shown in FIG. 5. In many embodiments, the first voltage storage device C1, the second voltage storage device C21, and the third voltage storage device C22 are capacitors. Useful capacitors include, for example, NMOS/PMOS capacitors, MIM capacitors, and vertical natural capacitors, among others.

A differential sense amplifier (an illustrative schematic diagram is shown in FIG. 8) is electrically coupled to the first voltage storage device C1 and is electrically coupled to an intermediate node electrically between the second voltage storage device C21 and the third voltage storage device C22. The differential sense amplifier is configured to compare the first bit line voltage V_(BL1) with the second bit line voltage V_(BL2). A first switch transistor STL1 is electrically connected to the bit line BL and the first voltage storage device C1. A second switch transistor STL2 is electrically connected to the bit line BL and the second voltage storage device C21 and the third voltage storage device C22. In many embodiments, the voltage storage devices are capacitors. In many embodiments, the second voltage storage device C21 and the third voltage storage device C22 are capacitors that each has substantially the same capacitance value as each other.

A first read current I_(R1) is applied and incurs the corresponding BL voltage V_(BL1), which is stored in C1. Depending on the resistance state of the MTJ, V_(BL1) can be either V_(BL, L1) or V_(BL, H1), which are the BL voltage for low resistance state of MTJ or high resistance state of MTJ, at I_(R1). A second read current I_(R2) which is larger than I_(R1) is applied and incurs BL voltage V_(BL2), which is stored in C21 and C22.

By comparing V_(BL1) and V_(BL2) with the differential sense amplifier, the data resistance state of the MTJ can be readout. For example, if the first bit line read voltage V_(BL1) is not substantially the same as or is larger than or significantly larger than the second bit line read voltage V_(BL2) then the first resistance state is determined to be a high resistance state. Accordingly, if the first bit line read voltage V_(BL1) is substantially the same as or less than the second bit line read voltage V_(BL2) then the first resistance state is determined to be a low resistance state.

In many embodiments, if the stored first bit line read voltage V_(BL1) is 10% greater than, or 25% greater than, or 50% greater than, or 100% greater than, the stored second bit line read voltage V_(BL2) then the first resistance state is determined to be a high resistance state. Otherwise the resistance state is determined to be a low resistance state.

FIG. 6 is a graph of I-R curves of the MTJ high resistance state and low resistance state. The reference points R_(L1) and R_(L2) refer to the low resistance values (data state “0”) of the MTJ at the first read current I_(R1) and the second read current I_(R2), respectively. The reference points R_(H1) and R_(H2) refer to the high resistance values (data state “1”) of the MTJ at the first read current I_(R1) and the second read current I_(R2), respectively. The value ΔR_(LMAX) refers to the change in the MTJ low resistance value from zero to the maximum allowable read current I_(RMAX). The value ΔR_(HMAX) refers to the change in the MTJ high resistance value from zero to the maximum allowable read current I_(RMAX).

As illustrated in FIG. 6, the resistance of the magnetic tunnel junction data cell MTJ at the low resistance state is fairly insensitive to the change of read current/voltage. On the other hand, the resistance of the magnetic tunnel junction data cell MTJ at the high resistance state drops quickly when the read current/voltage increases. The change in the high state resistance value from the first read current I_(R1) to the second read current I_(R2) is shown as ΔR_(H). The change in the low state resistance value from the first read current I_(R1) to the second read current I_(R2) is shown as ΔR_(L). As illustrated, ΔR_(L) is significantly less than ΔR_(H). Knowing that ΔR_(L) is significantly less than ΔR_(H) provides a means for comparing the voltage or resistance across the magnetic tunnel junction data cell MTJ to determine if it is in the high or low resistance state.

In many embodiments, I_(R2), is chosen to be I_(RMAX). The first read current I_(R1) is less than the second read current. In many embodiments, the first read current I_(R1) is 40% to 60% of the second read current I_(R2). In many embodiments, the first read current L_(H) is 40% to 50% of the second read current I_(R2).

FIG. 7 is a schematic circuit diagram of an illustrative adjustable current driver. FIG. 8 is a schematic circuit diagram of an illustrative differential sense amplifier. FIG. 9 is a timing diagram for the illustrative spin-transfer torque MTJ memory apparatus of FIG. 5.

In FIG. 9 the horizontal axis is the time axis. At the time of the 1^(st) read, the Decoder, first read current (I_(R1)), and first switch transistor (STL1) are all activated and the differential sense amplifier output (SA_OUT) is indicated as a result of the voltage stored in the first voltage storage device. The 1^(st) read, Decoder, first read current (I_(R1)), first switch transistor (STL1) are then all deactivated prior to the 2^(nd) read. At the time of the 2^(nd) read the 2^(nd) read, Decoder, second read current (I_(R2)), and second switch transistor (STL2) are all activated and the differential sense amplifier output (SA_OUT) is indicated as a result of the voltage stored in the second voltage storage device. The 2^(nd) read, Decoder, second read current (I_(R2)), second switch transistor (STL2) are then all deactivated prior to the differential sense amplifier activation SA Enable to compare the first bit line voltage with the second bit line voltage as described above.

FIG. 10 is a flow diagram of an illustrative self-reference reading method. The method includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state at block M1 and storing the first bit line read voltage in a first voltage storage device at block M2. A second read current is applied thorough the first resistance state magnetic tunnel junction data cell to form a second bit line read voltage, where the first read current is less than the second read current at block M3 and storing the second bit line read voltage in a second voltage storage device and third voltage storage device at block M4. Then comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state at block M5.

The comparing block C1 compares the first bit line read voltage (V_(BL1)) with the second bit line read voltage (V_(BL2)). If the first bit line read voltage (V_(BL1)) is greater than the second bit line read voltage (V_(BL2)) then the first resistance state of the magnetic tunnel junction data cell is a high resistance state at block D1. If the first bit line read voltage (V_(BL1)) is not greater than the second bit line read voltage (V_(BL2)) then the first resistance state of the magnetic tunnel junction data cell is a low resistance state block D2.

The comparing step includes comparing the first bit line read voltage with the second bit line read voltage and if the first bit line read voltage is greater than or is significantly greater than the second bit line read voltage then the first resistance state is determined to be a high resistance state. Accordingly, if the first bit line read voltage is substantially the same as or less than the second bit line read voltage then the first resistance state is determined to be a low resistance state.

Thus, embodiments of the SELF-REFERENCE NON-DESTRUCTIVE SPIN-TRANSFER TORQUE MEMORY are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow. 

What is claimed is:
 1. A spin-transfer torque memory apparatus comprising: a magnetic tunnel junction data cell electrically between a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; an adjustable current driver electrically coupled to the bit line, the adjustable current driver configured to provide a provide a first read current and a second read current through the magnetic tunnel junction data cell, the first read current being less than the second read current; a first voltage storage device electrically coupled to the bit line and configured to store a first bit line voltage formed by the first read current; a second voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current; and a differential sense amplifier electrically coupled to the first voltage storage device and electrically coupled to the second voltage storage device, the differential sense amplifier configured to compare the first bit line voltage with the second bit line voltage.
 2. A spin-transfer torque memory apparatus according to claim 1, wherein the first voltage storage device is a capacitor and the second voltage storage device is a capacitor.
 3. A spin-transfer torque memory apparatus according to claim 2, further comprising a third first voltage storage device electrically in series with the second voltage storage device.
 4. A spin-transfer torque memory apparatus according to claim 3, wherein the third voltage storage device is a capacitor.
 5. A spin-transfer torque memory apparatus according to claim 2, wherein the first voltage storage device and the second voltage storage device are NMOS or PMOS capacitors.
 6. A spin-transfer torque memory apparatus according to claim 4, wherein the third voltage storage device is a NMOS or PMOS capacitor.
 7. A spin-transfer torque memory apparatus according to claim 4, the second voltage storage device has a second capacitance value and the third voltage storage device has a third capacitance value and the second capacitance value is substantially the same as the third capacitance value.
 8. A spin-transfer torque memory apparatus according to claim 3, wherein the first voltage storage device and the second voltage storage device is a capacitor are in electrical parallel relation to each other.
 9. A spin-transfer torque memory apparatus according to claim 3, wherein the differential sense amplifier electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device.
 10. A memory apparatus comprising: a magnetic tunnel junction data cell electrically between a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell; an adjustable current driver electrically coupled to the bit line, the adjustable current driver configured to provide a provide a first read current and a second read current through the magnetic tunnel junction data cell, the first read current being less than the second read current; a first voltage storage device electrically coupled to the bit line and configured to store a first bit line voltage formed by the first read current; a second voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current; a third voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current, the second voltage storage device and the third voltage storage device are electrically connected in series; and a differential sense amplifier electrically coupled to the first voltage storage device and electrically coupled to the second voltage storage device, the differential sense amplifier configured to compare the first bit line voltage with the second bit line voltage.
 11. A memory apparatus according to claim 10, wherein the first voltage storage device is a capacitor and the second voltage storage device is a capacitor.
 12. A memory apparatus according to claim 10, wherein the third voltage storage device is a capacitor.
 13. A memory apparatus according to claim 11, wherein the first voltage storage device and the second voltage storage device are NMOS or PMOS capacitors.
 14. A memory apparatus according to claim 12, wherein the third voltage storage device is a NMOS or PMOS capacitor.
 15. A memory apparatus according to claim 12, the second voltage storage device has a second capacitance value and the third voltage storage device has a third capacitance value and the second capacitance value is substantially the same as the third capacitance value.
 16. A memory apparatus according to claim 10, wherein the first voltage storage device and the second voltage storage device is a capacitor are in electrical parallel relation to each other.
 17. A memory apparatus according to claim 10, wherein the differential sense amplifier electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device. 